| 摘要 |
A drive circuit of a display unit has a control circuit and a plurality of source drivers that are cascade-connected to each other. A start pulse signal is inputted into the source driver at the first stage and digital image data signals and clock signals are inputted into the source drivers at the respective stages from the control circuit. Clock signals are generated by a clock control circuit of the control circuit. For the clock signals, a reading period and a transferring period appear alternately, and the frequency of the low frequency clock pulse signal in the transferring period is lower than that of the high frequency clock pulse signal in the reading period. A shift register of the source driver transfer the start pulse signal to said source driver at the next source driver within one transferring period, and the start pulse signal is thus transferred in order from the source driver at the first stage up to the source driver at the final stage. Then, the source driver inputted the start pulse signal reads the digital image data signals in the reading period.
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