A MEMORY CELL FOR EMBEDDED MEMORIES

摘要

A memory cell comprising an inverting stage, an access transistor coupled between a data line and an input of the inverting stage, the access transistor being responsive to a control signal for selectively coupling the data line and the inverting stage input, a feedback transistor coupled to the inverting stage input and being responsive to an output of the inverting stage for latching the inverting stage in a first logic state and whereby the cell is maintained in a second logic state by a leakage current flowing through the access transistor which is greater tha n a current flowing through the feedback transistor.