| 摘要 |
A power output circuit having a pulse-width modulation generator and an upstream closed-loop control circuit which switches the pulse-width modulation generator and the power output stage to a permanently open mode, a PWM mode having pulse-width-modulated pulses, and a permanently closed mode as a function of a preset external setpoint, an actual value of the power output stage, and a reference voltage derived from the supply voltage. High power loss and high EMC in the full-load threshold region are avoided by prematurely switching from the PWM mode to the permanently closed mode as a function of a preset setpoint and the supply voltage, and returning to the PMW mode with a hysteresis of these values.
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