| 摘要 |
<p>PROBLEM TO BE SOLVED: To provide a synchronizing device for enabling data transfer by synchronizing devices at different clock rates. SOLUTION: Pipeline processing of data is performed between two clocks. Respective plural synchronizing device stages are provided with data registers 601-605 and synchronizing circuits 611-615. The synchronizing circuit synchronizes the write request signal of a first clock and a second clock signal. On one synchronizing device stage, corresponding to a write pointer 625, data are written by receiving the write request signal of the first clock, the write pointer is incremented, and the next synchronizing device stage is displayed. When the output is synchronized with the second clock signal by a read pointer 635, the displayed read stage extracts data from the correspondent data register, the read pointer is incremented, and the next synchronizing device stage is displayed. Plural first domain write request signals are in the various states of being simultaneously synchronized with the second clock signal on the correspondent synchronizing device stages.</p> |
