Asymmetric semiconductor memory device having electrically floating body transistor

摘要

Asymmetric, semiconductor memory cells, arrays, devices and methods are described. Among these, an asymmetric, bi-stable semiconductor memory cell is described that includes: a floating body region configured to be charged to a level indicative of a state of the memory cell; a first region in electrical contact with the floating body region; a second region in electrical contact with the floating body region and spaced apart from the first region; and a gate positioned between the first and second regions, such that the first region is on a first side of the memory cell relative to the gate and the second region is on a second side of the memory cell relative to the gate; wherein performance characteristics of the first side are different from performance characteristics of the second side.

主权项

1. An asymmetric semiconductor memory cell comprising:
a floating body region having a first conductivity type selected from n-type conductivity type and p-type conductivity type; said floating body region comprising means for storing a charge or lack of charge as a volatile memory indicative of a state of the asymmetric semiconductor memory cell; a first region having said first conductivity type, wherein said first conductivity type of said first region is and being in direct contact with said first conductivity type of said floating body region; a gate positioned above said floating body region; and a second region in electrical contact with said floating body region and spaced apart from said first region, said second region having a second conductivity type selected from said n-type and said p-type conductivity type, said second conductivity type being different from said first conductivity type.