发明名称 BOOSTING CIRCUIT AND SEMICONDUCTOR MEMORY
摘要 <p>PROBLEM TO BE SOLVED: To provide a word line boosting circuit of which boosting voltage is adjusted in a range of the upper limit value and the lower limit value of distribution of threshold voltage of a semiconductor non-volatile memory element independently of a value of power source voltage. SOLUTION: The number of parallel connection of capacitors provided respectively by plural boosting stages being connected directly in a drain side boosting circuit VCa are varied in accordance with a value of power source voltage Vcc. In detection of power source voltage Vcc, resistance-divided voltage values are detected by comparators OP1-OP3. And operation signals S1a-S3a are generated by a decoder DCa depending on combination of output of the comparators OP1-OP3, and it is decided which capacitors are connected parallel.</p>
申请公布号 JP2001273784(A) 申请公布日期 2001.10.05
申请号 JP20000090512 申请日期 2000.03.29
申请人 MITSUBISHI ELECTRIC CORP 发明人 OGURA TAKU
分类号 G11C16/06;G11C5/14;H02M3/07;(IPC1-7):G11C16/06 主分类号 G11C16/06
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