| 摘要 |
<p>PROBLEM TO BE SOLVED: To test a high-speed clock recovery operation with respect to an LSI used by the receiving side of a digital communication, using an LSI tester which is relatively low-speed and inexpensive. SOLUTION: A testing device 4 has a pseudorandom number generating circuit 42 for generating pseudorandom numbers on the basis of, e.g. a 125 MHz clock outputted from a clock multiplication circuit 11 in a clock recovery circuit 1 and an expected value generating/collating circuit 44 for collating 125 Mbps reproduced data outputted from the circuit 1 with the expected value data, for instance, by 5 or 15 bits each at a time and outputting the results as a 1-bit test output. Even though 4 actually the circuit 1 in the LSI and the device operate, e.g. with a 125 MHz high-speed clock, such a test output as is recognized as 25 MHz low-speed data form the outside of the LSI is outputted to the outside.</p> |
