发明名称 Digital phase locked loop circuit
摘要 A digital PLL circuit, which can realize a high accurate hold-over function even in case that power supply voltage or ambient temperature is changed, is provided. The digital PLL circuit provides a first, a second and a third loop circuits. In the third loop circuit, an adder and a differentiator calculate a difference between a frequency of a signal outputted from a fixed frequency oscillator and an output frequency, and a memory circuit memorizes the difference calculated at the adder and the differentiator, and another adder compares the difference between the frequency of the signal outputted from the fixed frequency oscillator and a current output frequency with the difference memorized in the memory circuit. And a frequency of a signal outputting from a voltage controlled oscillator (VCO) is controlled by the compared result.
申请公布号 US6384650(B1) 申请公布日期 2002.05.07
申请号 US20000560144 申请日期 2000.04.28
申请人 NEC CORPORATION 发明人 FUKUNAGA SEIJI;SATO YASUHIRO
分类号 H03L7/06;H03L7/087;H03L7/14;(IPC1-7):H03L7/06 主分类号 H03L7/06
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