| 摘要 |
PROBLEM TO BE SOLVED: To provide an SGT manufacturing method which reduces parasitic capacitance between gate wiring and a substrate and which is a gate last process; and provide an SGT structure.SOLUTION: A semiconductor device manufacturing method comprises: a step of forming a fin-shaped silicon layer on a silicon substrate and forming a first insulation film around the fin-shaped silicon layer and forming a columnar silicon layer above the fin-shaped silicon layer; a step of implanting an impurity on the columnar silicon layer and on the fin-shaped silicon layer and under the columnar silicon layer to form diffusion layers; a step of forming a gate insulation film, a polysilicon gate electrode and polysilicon gate wiring; a step of forming a silicide on the diffusion layer on the fin-shaped silicon layer; a step of depositing an interlayer insulation film and exposing the polysilicon gate electrode and the polysilicon gate wiring, and etching the polysilicon gate electrode and the polysilicon gate wiring, and subsequently depositing metal to form a metal gate electrode and metal gate wiring; and a step of forming contacts.SELECTED DRAWING: Figure 1 |
