发明名称 MULTILAYER WIRING BOARD
摘要 <p>PROBLEM TO BE SOLVED: To prevent the increase in capacitance of a built-in capacitor due to simultaneous baking by adjusting the material composition of a high dielectric layer and low dielectric layer. SOLUTION: In a multilayer wiring board in which a conductive wiring layer 2 is arranged on the surface of the inside of a ceramic insulating substrate 1 which is a laminate of a high dielectric layer 1b and low dielectric layers 1a and 1c, the layer 1b contains CaTiO3 and the amount of Ca in the layers 1a and 1c is set at 20% or more of the total amount of Ca in the layer 1b. By the way, both layers 1a and 1c are preferably made of sintered bodies obtained by adding an inorganic filler to an SiO2 -BaO-CaO-Al2 O3 -B2 O3 based glass and sintering the resulting bodies.</p>
申请公布号 JP2002290053(A) 申请公布日期 2002.10.04
申请号 JP20010093564 申请日期 2001.03.28
申请人 KYOCERA CORP 发明人 SUZUKI SHINICHI;NAGAE KENICHI;NAKAO YOSHIHIRO
分类号 H05K3/46;H01L23/12;H01L23/15;(IPC1-7):H05K3/46 主分类号 H05K3/46
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