| 摘要 |
PURPOSE: An output driving circuit is provided, which is designed to obtain an optimum speed at every x16, x8 and x4 by varying sizes of a buffer and a driver connected to each output port. CONSTITUTION: An enable signal calculation part(100) outputs a control signal(con), while selects an operable buffer part(200) by receiving and calculating an output enable signal(OE) of a possible output type. The buffer part outputs the first and the second data selection signal(sell1, sell2) by receiving the above control signal. And a driver part(300) outputs a data output signal(data_out) by receiving the first and the second data selection signal.
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