CACHE MEMORY AND MICROPROCESSOR USING THE SAME

摘要

PURPOSE: A cache memory and a microprocessor using the same are provided to offer a command cache of the low electric power consumption while not increasing the complexity of a circuit comparing to the conventional cache. CONSTITUTION: The command cache includes a line reuse buffer(201) and a cache controller(202) controlling an operation of the entire cache including the line reuse buffer(201). The command cache includes a multiplexer(203) configuring a data path relating to the line reuse buffer(201), a state display(207) displaying a state of the cache controller(202), a logical sum gate(209) deciding the cache hit, and the logical sum gate(211) generating a chip selection signal for a main memory and a tag memory. The cache controller(202) decides whether an executing engine approaches to a cache line in the line reuse buffer(201) at a next cycle by integrating the sequential fetch information provided by the executing engine during the same cycle and a position of the approaching data on the cache line.