| 摘要 |
A non-volatile memory structure having a higher gate-coupling ratio. The structure includes a substrate, shallow trench isolation layers, buried source/drain terminals, tunnel oxide layers, a floating gate with a three-dimensional structure, dielectric layers and a control gate. A portion of the floating gate is located inside an opening in the dielectric layer so that a three-dimensional structure formed. Since the subsequently formed control gate has a larger effective surface area, a higher gate-coupling ratio is obtained.
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