| 摘要 |
A configuration memory architecture for an FPGA eliminates the need for a regular array of word lines and bit lines. The memory includes memory bytes, each of which has eight SRAM latches, a single flip-flop and a one-of-eight decoder having data input coupled to the inverting output of the flip-flop and eight individual data outputs, each of which is coupled to a data input of one of the SRAM latches. The flip-flops of all memory bytes for a logic block are coupled together in a serpentine shift register. Loading of configuration data involves shutting down all paths through the decoder, shifting all configuration bits for the "0" position SRAM latch of each memory byte into the shift register, and setting the address bits to the decoder so as to create a conductive path on each memory byte from the output of the flip-flop to the data input of the 0 latch. The process is then repeated for the seven other SRAM latch positions.
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