发明名称 ATM COMMUNICATION CONTROLLER
摘要 <p>PROBLEM TO BE SOLVED: To reduce the number of connections of UTOPIA buses for connecting an ATM layer device to a PHY layer device. SOLUTION: Each control signal of a UTOPIA bus 2, for connecting an ATM layer device 1 to a PHY layer device 3, is shared by reception side processing and transmission side processing, and the transmission side processing and the reception side processing are switched alternately through time-division. In this case, the switching timing of PHY output enable to disable and the switching timing of ATM output disable to enable are executed respectively, at the rising and falling of a clock with a fixed time interval, far avoiding collision of the mutual output signals at switching.</p>
申请公布号 JP2003018190(A) 申请公布日期 2003.01.17
申请号 JP20010199170 申请日期 2001.06.29
申请人 NEC MIYAGI LTD 发明人 OSADA RYOICHI
分类号 H04L12/70;H04L29/10;(IPC1-7):H04L12/56 主分类号 H04L12/70
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