| 摘要 |
Briefly, a processor-based device, such as a microcontroller, provides a data bus that is shared by both non-volatile memory and volatile memory. The processor-based device also provides specialized signals to facilitate the data bus sharing. A non-volatile memory controller of the processor-based device provides a non-volatile memory busy signal and a non-volatile memory request signal to a volatile memory controller of the processor-based device. The non-volatile memory busy signal indicates to the volatile memory controller when the non-volatile memory controller controls the data bus. The non-volatile memory request signal indicates to the volatile memory controller when the non-volatile memory controller needs to use the data bus. The volatile memory controller provides a volatile memory busy signal to the non-volatile memory controller which informs the non-volatile memory controller when the data bus is controlled by the volatile memory controller. By providing the non-volatile memory busy signal, the non-volatile memory request signal and the volatile memory busy signal, a processor-based device can effectively support a data bus shared by a non-volatile memory and a volatile memory. The volatile-memory controller can include a write buffer and a volatile-memory arbiter having a write buffer state and a processor bus master state. Transactions to volatile memory or non-volatile memory use a processor bus in addition to the shared data bus. When the volatile-memory arbiter is in the write buffer state, the write buffer can initiate a write buffer cycle using the shared data bus. When the volatile-memory arbiter is in the write buffer state and a non-volatile memory request signal is asserted, the volatile-memory arbiter transitions to the processor bus master state. In the processor bus master state, the write buffer cannot initiate a write buffer cycle. In this way, collisions between write buffer accesses to the volatile memory and accesses to the non-volatile memory are avoided.
|
