发明名称 DELAY ADJUSTMENT CELL
摘要 <p>PROBLEM TO BE SOLVED: To adjust the timing of circuit action of a semiconductor integrated circuit by performing delay adjustment for wiring delay, without changing the wiring resource. SOLUTION: The driving capacity can be controlled; by adjusting the number of inverters for drive by setting the input values of a plurality of drive capacity switching terminals (cpx and cnx), provided in a delay adjusting cell 1, when a timing error occurs in a semiconductor integrated circuit; thus the timing of the circuit action of the semiconductor integrated circuit can be adjusted by performing the delay adjustment for wiring delay, without changing the wiring resource.</p>
申请公布号 JP2003060487(A) 申请公布日期 2003.02.28
申请号 JP20010243054 申请日期 2001.08.10
申请人 MATSUSHITA ELECTRIC IND CO LTD 发明人 YAMAMOTO ATSUSHI;NARUSE TATSUYA
分类号 H03K5/14;(IPC1-7):H03K5/14 主分类号 H03K5/14
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