Stacked NMOS device biasing on MOS integrated circuits and methods therefor

摘要

An integrated NMOS circuit including an active stack having a plurality of isolated p-well active devices M1-M3, aode-connected isolated p-well bias devices M4-M6, isolated p-well bias devices M4-ed isolated p-well bias devices coupled to the gatality of diode-connected isolated p-well bias devited p-well active devices, the bulk of each of thethe plurality of isolated p-well active devices, t devices coupled directly to the bulk of the corred isolated p-well bias devices coupled directly toctive devices, and the source of each of the pluray of isolated p-well active devices, and the sources coupled directly to the bulk of the correspondiated p-well bias devices coupled directly to the bulk of the corresponding diode-connected isolated p-well bias device.