Calculating circuit for dividing a fixed-point signal

摘要

1. A calculating circuit for dividing a fixed-point input signal consisting of a sequence of n-bit-wide digital data values by an adjustable dividing factor 2a for generating a divided fixed-point output signal, comprising: a signal input (2) for applying the data value sequence of the fixed-point input signal; a first addition circuit (6) which adds the digital data value present at the signal input (2) to a data value temporarily stored in a register (33) to form a max(n,a+1)+1-bit-wide first aggregate digital data value; a shift circuit (11) which shifts the first aggregate data value present by a data bits to the right so that the max(n,a+1)-a+1 higher-order data bits of the first aggregate data value are delivered at an output (12) of the shift circuit (11); a logic circuit (16) which logically ANDs the a lower-order data bits of the first aggregate data value with a logical data value in the case of a logically low output control signal of a control logic (53) and logically ORs these bits with the inverted logical data value in the case of a logically high output control signal of the control logic (53) and delivers them to the register (33) for temporarily storing the logically combined data value (dv1, dv2); a second addition circuit (37) which adds the data value delivered by the shift circuit (11) to a value one to form a second aggregate data value in the case of a logically high output control signal of the control logic (53); a signal output for delivering the sequence of the second aggregate data values as a divided fixed-point output signal; the control logic (53) delivering a logically high output control signal when the first aggregate data value is a negative number which cannot be divided by the dividing factor 2a without remainder.