发明名称 |
Method and apparatus for correcting the phase of a clock in a data receiver |
摘要 |
A method for correcting the phase of a clock in a data receiver which receives a data flow representing different signal levels with logical high and low signal values and signal transitions positioned therebetween, wherein the positions of such signal transitions between respective two adjacent logical signal values are evaluated for correcting the phase of the clock. The position of a signal transition between a first pair of signal values on one level (11) or a second pair of signal values on the other level (00) is weighted stronger in the evaluation then the positions of signal transitions between adjacent single signal values (1,0) of different signal levels.
|
申请公布号 |
US2003128779(A1) |
申请公布日期 |
2003.07.10 |
申请号 |
US20020042594 |
申请日期 |
2002.01.09 |
申请人 |
BERGER MATTHIAS;DORSCHKY CLAUS;HAUNSTEIN HERBERT;KUNZ FRANK;SCHULIEN CHRISTOPH;STICHT KONRAD |
发明人 |
BERGER MATTHIAS;DORSCHKY CLAUS;HAUNSTEIN HERBERT;KUNZ FRANK;SCHULIEN CHRISTOPH;STICHT KONRAD |
分类号 |
H03L7/089;H03L7/091;H04L7/033;(IPC1-7):H04L27/06 |
主分类号 |
H03L7/089 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|