| 摘要 |
PROBLEM TO BE SOLVED: To provide an MOS transistor of a further low ON resistance which can effectively use a region below a bonding pad, an MOS transistor of a lower ON resistance and a driver transistor of a low ON resistance by preventing a deterioration in characteristic from a layout designing stage by eliminating restrictions on an arrangement place of a bonding pad. SOLUTION: Since damage in a wire bonding process in a conventional technique is eliminated by adopting a CSP technique, restrictions on an arrangement plate of a pad is eliminated. Arrangement in a matrix is thereby possible, and parts of a transistor can be thereby miniaturized. Furthermore, since the length of a metal wiring in a transistor can be reduced, rise of ON resistance by a metal can be prevented. In the figure, 12 is polysilicon, 13 is a diffusion layer and 14 is a contact hole. COPYRIGHT: (C)2004,JPO |
