发明名称 Method of forming a reference voltage from a J-fet
摘要 A voltage reference circuit (20) has two J-FET transistors (22,25) that are formed to cooperate to supply a reference voltage that is stable over a wide range of supply voltages and temperatures. One transistor operates in the drain current saturation mode and the other transistor operates in a triode mode.
申请公布号 US2003231050(A1) 申请公布日期 2003.12.18
申请号 US20020171362 申请日期 2002.06.14
申请人 SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC 发明人 SUKUP FRANTISEK;HALAMIK JOSEF
分类号 G05F3/24;(IPC1-7):G05F1/10 主分类号 G05F3/24
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