| 摘要 |
<P>PROBLEM TO BE SOLVED: To attain stable clock recovery by detecting a lag / lead of a phase of a recovered clock at a converging point of a received signal so as to recover a clock. <P>SOLUTION: A clock recovery circuit 15 is provided with: a delay circuit 153 for storing N hard decision data resulting from sampling a received signal by a recovery clock; a comparison discrimination section 152 for comparing n-th hard decision data (1<n<N) among the N hard decision data stored in the delay circuit with preceding and succeeding hard decision data to the n-th hard decision data; an error detection section 154 for detecting a distance between soft decision data corresponding to the n-th hard decision data and a converging point of the soft decision data; and a sign decision section 155 for discriminating whether or not a detection output of the error detection section 154 is outputted as phase information to produce a recovery clock and its sign on the basis of a comparison output of the comparison discrimination section 152. <P>COPYRIGHT: (C)2004,JPO |
