| 主权项 |
1. A system for timing read operations with a memory device, the system comprising:
a gating circuit configured to receive a timing signal from the memory device and to pass through the timing signal as a filtered timing signal during a gating window, the gating circuit being configured to:
open the gating window based on a control signal, andclose the gating window based on a first edge of the timing signal, the first edge being determined based on a counter that is triggered to begin counting by the control signal, wherein the gating window is closed automatically based on an incrementing of the counter and without regard to the control signal; a timing control circuit configured to generate the control signal based on i) a count signal from the counter, and ii) a second edge of the timing signal that precedes the first edge in time; and a monitor circuit configured to determine a relationship between the timing signal and a pulse signal that is produced by the timing control circuit in response to a read request from a memory controller, wherein the monitor circuit includes:
a first module triggered to a falling edge of the timing signal, the first module being configured to read the pulse signal contemporaneously with the falling edge and generate a first output signal,a second module triggered to a rising edge of the timing signal, the second module being configured to read the pulse signal contemporaneously with the rising edge and generate a second output signal, anda third module triggered to a second falling edge of the timing signal, the third module being configured to read the pulse signal and the count signal from the counter contemporaneously with the second falling edge and generate a third output signal,wherein the relationship between the timing signal and the pulse signal is determined based on the first, second, and third output signals. |
