| 摘要 |
Two delay lines included in a DLL circuit receive clock signals complementary to each other to output complementary clock signals CLKP and CLKN for data output. A power supply generation circuit applying a power supply to the two delay lines is arranged at an equivalent position from the two delay line. An equal potential is supplied to the two delay lines by, for example, setting lengths of two power supply lines from a branch point equal to each other. By doing so, delay time of one delay line can be set equal to delay time of the other delay line and a phase error between clock signals CLKP and CLKN can be reduced. Therefore, a semiconductor device on which the DLL circuit having the improved phase error is mounted can be provided.
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