| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To provide a multiprocessor system preventing getting wrong data due to simultaneous access when transferring data between processors. <P>SOLUTION: An access bank control register 111 is provided to which control data is written by a first processor 101 determining which of a first bank 103 or a second bank 104 is accessed by own processor 101 or a second processor 102 and the control data can only be read from the second processor 102. Furthermore, a first memory controller 112 is provided making the first or the second processor possible to access only the first bank 103 which is allotted by the control data set to the access bank control register. Moreover, a second memory controller 113 is provided making the first or the second processor possible to access only the second bank 104 which is allotted by the control data set by the access bank control registor. <P>COPYRIGHT: (C)2004,JPO</p> |
