MULTIPLE LINE GRID AND HIGH-PERFORMANCE SEMICONDUCTOR PACKAGE USING THE SAME

摘要

PURPOSE: A multiple line grid is provided to control an increase of an interconnection line caused by a decoupling capacitor by installing a decoupling capacitor circuit electrically connected to a power terminal and a ground terminal of a semiconductor chip in a space region between a multiple line grid with a cavity or a substrate base guaranteed by the multiple line grid and a PCB(printed circuit board). CONSTITUTION: A cavity region(134) is formed inside a predetermined portion of a multiple line grid body(130). A plurality of main through holes(132) are located in the multiple line grid except the cavity region, penetrating and electrically connecting the upper and lower portions of the multiple line grid. A decoupling capacitor multiple line grid body(136) is disposed in the cavity region, separated from the multiple line grid body by a predetermined interval. A plurality of sub through holes(138) are located in the decoupling capacitor multiple line grid body, penetrating and electrically connecting the upper and lower portions of the multiple line grid.