| 摘要 |
A first memory cell block has memory cells connected together in series. Each of the memory cells comprises a cell transistor and a ferroelectric capacitor. The ferroelectric capacitor has an electrode at one end and an electrode at the other end which are connected to a source and a drain of the cell transistor, respectively. A first metal interconnect is connected between one end of the first block and one end of a current path in a first block selection transistor. A first bit line is connected to the other end of the current path in the first transistor. A second bit line is arranged adjacent to the first bit line. Second and third block selection transistors each have a current path one end of which is connected to the second bit line. Interconnects connected to gate electrodes of the second and third transistors are disposed below the first interconnect.
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