发明名称 Trace circuit
摘要 A trace circuit includes the event control circuit and two trace buffer memories. The event control circuit receives data on a control bus, an address bus, and data a bus and stores the data cyclically and alternately in the two buffer memories. Also, the event control circuit makes the two buffer memories output the stored data cyclically and alternately.
申请公布号 US6813732(B2) 申请公布日期 2004.11.02
申请号 US20010920930 申请日期 2001.08.03
申请人 RENESAS TECHNOLOGY CORP. 发明人 KUROOKA KAZUAKI;KANZAKI TERUAKI
分类号 G01R31/28;G06F11/22;G06F11/26;G06F11/28;H04B1/74;(IPC1-7):G06F11/00 主分类号 G01R31/28
代理机构 代理人
主权项
地址