| 摘要 |
In a phase-locked loop, multiple input clock references can each connect to a different interface card. Each interface card can include a phase comparator portion of a phase-locked loop. The phase comparators can produce a phase error signal for a phase-locked loop. One or more of the phase error signals can be transmitted across a bus, such as a time division multiplexed bus, to a system card. The system card can include a controlled oscillator portion of the phase-locked loop. The output of the system card can then sent back to one or more of the interface cards to complete the phase-locked loop.
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