| 摘要 |
A clock divider in a DLL circuit for generating an internal clock signal synchronized with an external clock signal includes; a first clock dividing circuit for generating a first signal clock by dividing an input clock signal having a same period as a period of the external clock signal, a second clock dividing circuit for generating both a second clock signal and a third clock signal by dividing the first clock signal, a selection signal generation circuit for generating a selection signal in response to plurality of control signals, and a clock signal selection circuit for selectively outputting the second clock signal or the third clock signal in response to the selection signal.
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