Hardware support for processing virtual machine instructions

摘要

The present disclosure includes systems and techniques relating to providing hardware support for processing virtual machine instructions. In some implementations, an apparatus, systems, or methods can include an interface for a system-on-chip (SOC), a memory device, a central processing unit (CPU) coupled with the interface and the memory device, where the CPU can be configured to process instructions defined by a first instruction set and to direct instructions defined by a second instruction set to the memory device, and processing hardware coupled with the interface and the memory device, where the processing hardware can be separate from the CPU and configured to retrieve and process the instructions defined by the second instruction set, and where the second instruction set can be different from the first instruction set, and the instructions defined by the second instruction set include code of a predefined virtual machine environment.

主权项

1. A system on an integrated circuit chip (SOC) for a storage device, the SOC comprising:
an interface for the SOC; a memory device that is separate from a central processing unit (CPU); a cache memory device that is separate from the memory device; the CPU coupled with the interface and the memory device, the CPU configured to process instructions defined by a first instruction set architecture and configured to write, to the memory device, bytecode representing instructions defined by a second instruction set architecture that is different from the first instruction set architecture, wherein the instructions defined by the second instruction set architecture conform to a predefined virtual machine environment; an interpreter, executed by the CPU, the interpreter configured to convert a scripting code, which conforms to the predefined virtual machine environment, to generate the bytecode representing the instructions defined by the second instruction set architecture; a cache memory manager, which is tightly coupled to the cache memory device, the cache memory manager configured to:
after the CPU has written the bytecode to the memory device and based on an instruction from the CPU, retrieves, at each memory cycle, stored bytecode from the memory device;writes, at each memory cycle, the stored bytecode to the cache memory device; and processing hardware coupled with the interface and the cache memory device, the processing hardware being separate from the CPU and configured to, after the cache memory manager has written the stored bytecode to the cache memory device, retrieve the stored bytecode from the cache memory device, and process the stored bytecode to execute the instructions in the predefined virtual machine environment to cause the processing hardware to perform a self-test of the storage device.