Intellectual property block design with folded blocks and duplicated pins for 3D integrated circuits

摘要

An intellectual property (IP) block design methodology for three-dimensional (3D) integrated circuits may comprise folding at least one two-dimensional (2D) block that has one or more circuit components into a 3D block that has multiple tiers, wherein the one or more circuit components in the folded 2D block may be distributed among the multiple tiers in the 3D block. Furthermore, one or more pins may be duplicated across the multiple tiers in the 3D block and the one or more duplicated pins may be connected to one another using one or more intra-block through-silicon-vias (TSVs) placed inside the 3D block.

主权项

1. A method for designing an integrated circuit, comprising:
folding a two-dimensional (2D) block that has one or more circuit components into a three-dimensional (3D) block having multiple tiers, wherein the one or more circuit components in the folded 2D block are distributed among the multiple tiers in the 3D block; duplicating one or more input/output (I/O) pin locations across the multiple tiers in the 3D block; and connecting the one or more duplicated I/O pin locations using one or more intra-block through-silicon-vias (TSVs) placed inside the 3D block.