发明名称 |
Mass production process of high voltage and high current Schottky diode with diffused design |
摘要 |
A process of manufacture of high voltage (300-600V) and high current (10-100 A) Schottky diode, which includes the following steps in sequence: provide a N-type silicon wafer; process phosphor deposition and high-concentration N+ phosphorus diffusion; cutting and chemical mechanical polishing; classifying into different voltage groups; processing primary oxidation and lithography; processing boron diffusion, secondary lithography and wiring; process ion implantation and metal spluttering to form the Schottky barrier; process metal evaporation and lithography for front metal; and finally process etching and metal evaporation for rear metal. Instead of the conventional epitaxial process, a diffusion process is employed to form the N+ layer. The final product is equipped with the advantages of Schottky diode and is applicable for high voltage of 300-600V and high current of 10-100 A. The current leakage and defect rate are dramatically lowered while the cost is lowered, thus mass production is facilitated. |
申请公布号 |
US9502522(B1) |
申请公布日期 |
2016.11.22 |
申请号 |
US201615056673 |
申请日期 |
2016.02.29 |
申请人 |
Chongqing Pingwei Enterprise Co., Ltd. |
发明人 |
Wang Xinglong;Li Shuzhou;Zhang Li;Xu Xiangtao |
分类号 |
H01L29/872;H01L29/66;H01L21/304;H01L29/47;H01L21/225;H01L21/78;H01L21/306;H01L21/265;H01L21/285;H01L21/66;H01L29/861;H01L21/302 |
主分类号 |
H01L29/872 |
代理机构 |
Novoclaims Patent Services LLC |
代理人 |
Novoclaims Patent Services LLC ;Wong Mei Lin |
主权项 |
1. A process of manufacturing high voltage and high current Schottky diode with diffused design, comprising the sequential steps of:
(a) selecting a raw N-type silicon wafer; (b) processing phosphor deposition for a surface of the raw N-type silicon wafer to form a high-concentration phosphorus layer on the surface; (c) processing high-concentration N+ phosphorus diffusion; (d) wire cutting the silicon wafer into two equal silicon units; (e) processing chemical mechanical polishing (CMP) for at least one of the silicon units; (f) classifying the silicon unit into one of different preset voltage groups; (g) processing primary oxidation; (h) processing primary lithography; (i) processing boron diffusion to form a p-type diffusion layer; (j) processing secondary lithography for a wiring hole; (k) processing ion implantation to form p+ layer; (l) processing metal sputtering; (m) forming Schottky barrier; (n) processing metal evaporation for front side; (o) processing lithography for front metal; (p) processing etching for rear side; and (q) processing metal evaporation for rear side. |
地址 |
Chongqing CN |