Parallel bit test circuit in semiconductor memory device and associated method

摘要

An embodiment is a circuit including 2^n-1 first comparators to generate a first result by comparing data from at least two of 2ⁿ memory cells to which test pattern data are written. 2^n-1 first switching circuits provide the first result or a disable signal responsive to a first switching signal. And 2^n-2 second comparators generate a second result by comparing signals output from some of the 2^n-1 first switching circuits. N may be a natural number greater than or equal to three.