| 摘要 |
A frequency synthesiser 50 comprises a VCO 56 whose output signal frequency is proportional to input voltage amplitude. In a first mode, the VCO output is fed via a divider 24 to a phase detector 26 which also receives a reference signal. The phase detector output passes via a loop filter 28 and a controller 70, which is passive in the first mode, back to the VCO 56 to form a closed phase-locked loop. To adjust the frequency synthesiser output frequency, the controller 70 switches the circuit into a second mode in which the VCO 56 output is not fed back, and a constant voltage source is supplied to the VCO 56 instead so that the VCO output frequency is constant. The VCO transfer function is then altered by adjusting a variable capacitor 60 therein, and the circuit is then switched back to the first mode. The locking time of the synthesiser is thereby improved as output frequency changes.
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