发明名称 |
RECEIVER, CLOCK ADJUSTMENT METHOD, AND BROADCAST SYSTEM |
摘要 |
<p><P>PROBLEM TO BE SOLVED: To provide a receiver or the like capable of suppressing frequency of the occurrence of overflow and underflow in a reception buffer thereby improving the stability of data reception. <P>SOLUTION: The receiver 2 for receiving digital data from a transmitter 1 via a network 3 includes: a receiver side clock 56; a reception buffer 35; a reception buffer monitoring section 37; and an adjustment section 53. The receiver side clock 56 generates a clock signal at a prescribed time interval for processing digital data. The reception buffer 35 stores the digital data. The reception buffer monitoring section 37 monitors a data storage amount in the reception buffer 35. The adjustment section 53 adjusts the time interval to generate the clock signal on the basis of a relationship between the data storage amount at the start of a determination time interval and a data storage amount after the determination time interval when variations in the data storage amount are kept within a prescribed range during the determination time interval. <P>COPYRIGHT: (C)2006,JPO&NCIPI</p> |
申请公布号 |
JP2006114988(A) |
申请公布日期 |
2006.04.27 |
申请号 |
JP20040297854 |
申请日期 |
2004.10.12 |
申请人 |
TOA CORP |
发明人 |
SUZUKI AKIHIRO |
分类号 |
H04L13/08;H04L7/00;H04L12/885;H04L29/08 |
主分类号 |
H04L13/08 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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