发明名称 CONTROL BLOCK SIZE REDUCTION THROUGH IP MIGRATION IN AN INTEGRATED CIRCUIT DEVICE
摘要 Methods for control block size reduction of a controller of an integrated circuit (IC) device through intellectual property (IP) migration in the IC device are disclosed. A disclosed method includes receiving configuration data for the IC device and determining whether IP construction data is defined in the configuration data. The IP construction data contains instruction sets for implementing logical operations of a controller-based IP core in a core region of the IC device. Such data creates flexibility to configure the controller-based IP core in a core logic circuit as a soft IP core, when required. In this scenario, the controller-based IP core can be removed from the controller of the IC device during IC device fabrication. As a result, the footprint (e.g., area) of the controller of the IC device can be reduced, which subsequently increases cost-savings for the IC device fabrication.
申请公布号 US2017098026(A1) 申请公布日期 2017.04.06
申请号 US201514872989 申请日期 2015.10.01
申请人 Altera Corporation 发明人 Ew Chee Yong
分类号 G06F17/50 主分类号 G06F17/50
代理机构 代理人
主权项 1. A method of using a logic design system to generate configuration data for an integrated circuit (IC) device, the method comprising: receiving custom logic design data for the IC device; analyzing requirements of a controller for the IC device that is to be formed using the custom logic design data; identifying an intellectual property (IP) core associated with the controller; receiving an input selection corresponding to the identified IP core, wherein the input selection activates a soft IP configuration state for the IP core; and in response to an activation of the soft IP configuration state, generating the configuration data for the IC device, wherein the generated configuration data includes soft IP configuration data for the IP core, and wherein the soft IP configuration data configures an associated soft IP core in a core region of the IC device to implement logic functions of the IP core.
地址 San Jose CA US