发明名称 Configurable generic filter hardware block and methods
摘要 A configurable generic filter hardware block and corresponding methods are provided. A configurable generic filter hardware block includes a plurality of multipliers; a plurality of adders; and one or more multiplexers. The, configurable generic filter hardware block is configured using a header data structure, and the header data structure includes a pointer to a memory location storing a plurality of input samples, a pointer to a memory location storing a plurality of output samples and a coefficient selection control value. The configurable generic filter hardware block is optionally invoked by a convolution instruction in one or more of a vector processor and a state machine. An exemplary Generic Filter Iteration loads input samples; selects coefficients; convolves the input samples and the selected coefficients and stores output samples. The header data structures are optionally stored sequentially in memory and processed in a single loop.
申请公布号 US9621130(B2) 申请公布日期 2017.04.11
申请号 US201414318938 申请日期 2014.06.30
申请人 AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD. 发明人 Venkataraghavan Parakalan;Cheruvathery Sanal;Yu Meng-Lin M.;Williams Joseph
分类号 G06F17/10;H03H17/02 主分类号 G06F17/10
代理机构 Sheridan Ross P.C. 代理人 Sheridan Ross P.C.
主权项 1. A configurable filter hardware block, comprising: a plurality of multipliers; a plurality of adders connected to the plurality of multipliers; and one or more multiplexers connected to at least one of the plurality of adders, wherein said configurable filter hardware block is configured using a header data structure, said header data structure comprises a pointer to a memory location storing a plurality of input samples, a pointer to a memory location storing a plurality of output samples and a coefficient selection control value.
地址 Singapore SG