LOOP DELAY OPTIMIZATION FOR MULTI-VOLTAGE SELF-SYNCHRONOUS SYSTEMS

摘要

A clock-receiving system may receive a host clock signal on a communications bus from a clock-sending system. Circuitry of a critical path of the clock-receiving system may communicate the clock signal to a multiplexer configured directly behind output driver circuitry. Core logic circuitry and data path circuitry may communicate pairs of phase-shifted data signals to the multiplexer. The multiplexer may use the clock signal and the pairs of phase-shifted data signals to generate an output pair of data signals, and send the output pair of data signals to the output driver circuitry. In turn, the output driver circuitry may generate an output data signal for communication on the communications bus. The clock-receiving system may enable the critical path and use the multiplexer to generate the output data signal when in a low operating voltage mode.

主权项

1. A system comprising:
output driver circuitry configured to generate an output data signal for communication on a data line of a communications bus; path circuitry configured to generate a clock signal based on a host clock signal received on a clock line of the communications bus; and a multiplexer circuit configured to:
receive a plurality of multiplexer input data signals;receive the clock signal from the path circuitry;generate a pair of multiplexer output data signals based on the clock signal and the plurality of multiplexer input data signals; andoutput the pair of multiplexer output data signals to the output driver circuitry for generation of the output data signal.