METHOD AND STRUCTURE FOR PREVENTING EPI MERGING IN EMBEDDED DYNAMIC RANDOM ACCESS MEMORY

摘要

After forming a plurality of first semiconductor fins having a first spacing in a logic device region and a plurality of second semiconductor fins having a second spacing in a memory device region, sacrificial spacers are formed on sidewalls of the plurality of the first semiconductor fins and the plurality of the second semiconductor fins to completely fill spaces between the plurality of first semiconductor fins, but only partially fill spaces between second semiconductor fins. Next, dielectric barrier layer portions are formed in gaps between the sacrificial spacers. After removal of the sacrificial spacers, an entirety of the plurality of first semiconductor fins is laterally enclosed by a corresponding pair of neighboring dielectric barrier layers, while each of the plurality of second semiconductor fins is laterally enclosed by a corresponding pair of neighboring dielectric barrier layer portions.

主权项

1. A semiconductor structure comprising:
a plurality of first semiconductor fins having a first spacing and a plurality of second semiconductor fins having a second spacing located on a substrate, wherein the plurality of first semiconductor fins are spaced apart from the plurality of the second semiconductor fins; dielectric barrier layer portions located on the substrate, wherein an entirety of the plurality of first semiconductor fins are laterally enclosed by a corresponding pair of neighboring dielectric barrier layer portions, and wherein each of the plurality of the second semiconductor fins is laterally enclosed by a corresponding pair of neighboring dielectric barrier layer portions; a gate structure present on a channel portion of each of the plurality of first semiconductor fins and the plurality of second semiconductor fins; a first epitaxial semiconductor material portion present between adjacent first semiconductor fins in the plurality of first semiconductor fins to merge the plurality of first semiconductor fins, wherein the first epitaxial semiconductor material portion is in contact with vertical sidewalls of the corresponding pair of neighbor dielectric barrier layer portions that laterally encloses the entirety of the plurality of first semiconductor fins; and a second epitaxial semiconductor material portion present at least on sidewalls of each of the plurality of second semiconductor fins, wherein the second epitaxial semiconductor material portion is in contact with vertical sidewalls of the corresponding pair of neighbor dielectric barrier layer portions that laterally encloses each of the plurality of second semiconductor fins.