| 摘要 |
1450923 Adaptive equalisers PLESSEY CO Ltd 23 Sept 1974 [5 Oct 1973] 46733/73 Heading H4R In a data transmission system in which a receiver 3 includes an adaptive equaliser 5 which is selectively adjusted and has its output sampled for distortion equalisation, the sampling time of the equaliser output is varied in accordance with the error rate of the equaliser output in order to provide improved distortion equalisation. As described the equaliser output comprises a multi level analogue signal which is quantised and converted to 5 digit form, the first three digits representing the data information, the fourth digit providing an error signal Ve giving an error direction signal used to adaptively adjust the equaliser 5, while the fifth digit provides a further error signal which indicates whether the received level is nearer the mean value of the particular level or is nearer to the upper or lower limit of that particular level, and which is used to control the adaptive timing of the equaliser output-sampling. The sampling signal is derived from a pilot frequency fp received with the data signal and which is extracted by filter 11, Fig. 2, squared at 12, and used to control a phase locked oscillator 13. The phase of the sampling signal Pt relative the received pilot frequency is controlled by the output of d to a converter 17 connected to counter 16. The counter 16 is stepped each time an output is produced by the fifth bit counter 14, i.e. whenever a predetermined number of "fifth bits" of the quantised received signal have been determined as one, while the stepping direction of counter 16 is controlled to change each time the period between the outputs from the fifth bit counter reduces, indicating an increase in error, and is maintained to count in the same direction, either up or down, when the period between outputs from the fifth bit counter 14 increases, indicating a decrease in error. In order to provide a uniform rate output irrespective of the phase of sampling the sampled signals from the equaliser output are fed into an elastic store 7 and clocked out therefrom by the input Pc to the phase locked oscillator. During periods of gross errors, such as immediately after start-up the normal adaptive variation of timing is interrupted and the timing adjust counter is just scanned successively up and down until the error rate falls to a predetermined level. |
