发明名称 SETT ATT TIDSDOSERA OVERSTROMMAR I STROMRIKTARE SAMT ANORDNING FOR UTFORANDE AV SETTET
摘要 1470261 Automatic control of converters BBC BROWN BOVERI & CO Ltd 29 July 1974 [31 July 1973] 33393/74 Heading G3R A current regulator in a converter circuit receives a required value signal which can be increased above a maximum permissible level for a predetermined time. A time delay occurs automatically before the permissible level may be exceeded again. As shown in Fig. 1, a drive system includes a speed or voltage regulator 1 supplying a required current signal 2 for a subordinate current control loop including a regulator 8 receiving an input 7 from a comparator 3. In addition to the signal 2, the comparator receives an actual current signal 4 and also has a connection 6 to an additional current supply device 5, Fig. 2, which supplies a further current signal to the comparator if the required current signal 2 approaches a limit value. This situation is detected by a threshold device 51 which supplies a positive or negative signal as appropriate over a diode 52 or 53 to energize an output threshold device 59 which supplies additional current to the comparator 3 for a time which is set by the values of a resistor 58 and a capacitor 55 or 57. After the threshold switch 59 has reverted to its normal state, the production of a subsequent additional signal is inhibited for a time which is set by the value of a resistor 54 or 56. In another embodiment, Fig. 5 (not shown), the output of the additional current supply 5 is connected as a control signal for a pair of transistors connected in parallel with the feedback path of a regulating amplifier serving as the comparator 3.
申请公布号 SE389950(B) 申请公布日期 1976.11.22
申请号 SE19740009782 申请日期 1974.07.29
申请人 BBC AG BROWN;BOVERI & CIE 发明人 BERGMANN L
分类号 H02H7/08;H02M7/12;H02P7/28;(IPC1-7):02M1/18;02P13/16 主分类号 H02H7/08
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