Data transmission system error reduction circuit - verifies correct binary value of signal within specified time-slot compared with interference

摘要

The error-reduction circuit for data transmission systems subject to interference uses a test period of a certain length which is longer than the duration of any possible interfering signal. Only signals of the correct binary value, occuring within the specified time-slot, are allowed to pass to the data processing equipment. Each incoming data line is connected to a store and comparator which gives an output if each line has its correct binary value. The output of the store is connected to the comparator and a further register. The output of the comparator is connected to a multivibrator and, via an XOR gate, a D-type flip-flop. The non-inverted output of the flip-flop is connected to a channel control line.