Multilevel metallization for integrated circuits

摘要

The specification describes a procedure for multilevel metallization of semiconductor integrated circuits in which the severity of the step formed by the edges of the first level pattern and the intermediate insulator over which the second level metallization pattern extends is reduced by beveling the edge. The bevel occurs during selective etching of the first level metal as a consequence of depositing the first level metal over a range of diminishing temperatures. Metal layers, notably aluminum, deposited in this way exhibit a differential etch rate such that the layer etches more slowly as etching proceeds through the thickness of the layer. Bevels of the order of 30 DEG to the horizontal can be produced in this way.