| 摘要 |
Transistorized vertical deflection circuit employs output stage of class B, push-pull, complementary symmetry configuration. Miller integration approach is used for sawtooth wave generation, with feedback waveform derived from yoke current sampling resistor. Diode, coupled between ground and base of the (NPN) output transistor which conducts during retrace and first half of scan, operates in Zener region during retrace to hold voltage at joined emitters of output pair at s substantially constant voltage during retrace; output waveform is thereby stabilized against effects of B+ changes due to line voltage variations or loading extremes, and remaining (PNP) output transistor dissipation is held substantially constant in the face of such changes. Diode in feedback path, forward biased when retrace ends, ensures rapid turn-on of driver stage when discharge transistor cuts off; oppositely poled diode in shunt with first feedback diode completes low impedance capacitor discharge path during retrace. One winding half of vertical deflection yoke is shunted by a capacitor of a value selected to introduce cancellation of horizontal frequency components across yoke/pincushion circuitry, in order to minimize feedback of interlace-disturbing horizontal components in deflection circuit. |
