发明名称 Thin film transistor device (TFT) comprising stacked oxide semiconductor layers and having a surrounded channel structure
摘要 A semiconductor device having stable electric characteristics is provided. The transistor includes first to third oxide semiconductor layers, a gate electrode, and a gate insulating layer. The second oxide semiconductor layer has a portion positioned between the first and third oxide semiconductor layers. The gate insulating layer has a region in contact with a top surface of the third oxide semiconductor layer. The gate electrode overlaps with a top surface of the portion with the gate insulating layer positioned therebetween. The gate electrode faces a side surface of the portion in a channel width direction with the gate insulating layer positioned therebetween. The second oxide semiconductor layer includes a region having a thickness greater than or equal to 2 nm and less than 8 nm. The length in the channel width direction of the second oxide semiconductor layer is less than 60 nm.
申请公布号 US9461179(B2) 申请公布日期 2016.10.04
申请号 US201514788940 申请日期 2015.07.01
申请人 Semiconductor Energy Laboratory Co., Ltd. 发明人 Kobayashi Yoshiyuki;Matsuda Shinpei;Yamazaki Shunpei
分类号 H01L29/786;H01L29/36;H01L27/06;H01L29/04 主分类号 H01L29/786
代理机构 Fish & Richardson P.C. 代理人 Fish & Richardson P.C.
主权项 1. A transistor comprising: a first oxide semiconductor layer; a second oxide semiconductor layer over the first oxide semiconductor layer; a third oxide semiconductor layer over the second oxide semiconductor layer; a gate insulating layer over and in contact with the third oxide semiconductor layer; and a gate electrode over the gate insulating layer; wherein a portion of the gate electrode faces a side surface of the second oxide semiconductor layer in a channel width direction with the gate insulating layer positioned therebetween, wherein the portion of the gate electrode extends below a bottom surface of the second oxide semiconductor layer in a depth direction, wherein the second oxide semiconductor layer includes a region having a thickness greater than or equal to 2 nm and less than 8 nm, and wherein a length of the second oxide semiconductor layer in a channel width direction is less than 60 nm.
地址 Atsugi-shi, Kanagawa-ken JP