发明名称 |
Methods of increasing silicide to epi contact areas and the resulting devices |
摘要 |
One method disclosed includes, among other things, forming a gate structure above an active region of a semiconductor substrate, performing an epitaxial deposition process to form an epi semiconductor material on the active region in the source/drain region of the device, performing an etching process on the epi semiconductor material to remove a portion of the epi semiconductor material so as to define at least one epi recess in the epi semiconductor material, forming a metal silicide layer on the upper surface of the epi semiconductor material and in the at least one epi recess in the epi semiconductor material, and forming a conductive structure that is conductively coupled to the metal silicide layer. |
申请公布号 |
US9461171(B2) |
申请公布日期 |
2016.10.04 |
申请号 |
US201414283636 |
申请日期 |
2014.05.21 |
申请人 |
GLOBALFOUNDRIES Inc. |
发明人 |
Xie Ruilong;Kim Hoon;Moumen Naim;Park Chanro;Taylor, Jr. William J. |
分类号 |
H01L21/336;H01L29/78;H01L29/66;H01L29/417;H01L29/08;H01L21/768;H01L21/285;H01L23/485;H01L29/165 |
主分类号 |
H01L21/336 |
代理机构 |
Amerson Law Firm, PLLC |
代理人 |
Amerson Law Firm, PLLC |
主权项 |
1. A method of forming a transistor, said transistor having a gate structure and a source/drain region, the method comprising:
forming said gate structure above an active region of a semiconductor substrate; performing an epitaxial deposition process to form an epi semiconductor material on said active region in said source/drain region of said transistor, said epi semiconductor material having an upper surface; performing an etching process on said epi semiconductor material to remove a portion of said epi semiconductor material so as to define at least one epi recess in said epi semiconductor material, wherein said at least one epi recess abuts a sidewall spacer positioned adjacent said gate structure and exposes an outer surface portion of said sidewall spacer; after defining said at least one epi recess, exposing at least a portion of said upper surface of said epi semiconductor material adjacent said at least one epi recess; forming a metal silicide layer on said at least said exposed upper surface portion of said epi semiconductor material and in said at least one epi recess; and forming a conductive structure that is conductively coupled to said metal silicide layer. |
地址 |
Grand Cayman KY |