| 发明名称 | Semiconductor memory device for storing multivalued data | ||
| 摘要 | Data storage circuits are connected to the bit lines in a one-to-one correspondence. A write circuit writes the data on a first page into a plurality of 5 first memory cells selected simultaneously by a word line. Thereafter, the write circuit writes the data on a second page into the plurality of first memory cell. Then, the write circuit writes the data on the first and second pages into second memory cells adjoining 10 the first memory cells in the bit line direction. | ||
| 申请公布号 | US9460804(B2) | 申请公布日期 | 2016.10.04 |
| 申请号 | US201514861288 | 申请日期 | 2015.09.22 |
| 申请人 | KABUSHIKI KAISHA TOSHIBA | 发明人 | Shibata Noboru;Tanaka Tomoharu |
| 分类号 | G11C7/06;G11C16/34;G11C11/56;G11C16/04;G11C16/10;G11C16/12 | 主分类号 | G11C7/06 |
| 代理机构 | Oblon, McClelland, Maier & Neustadt, L.L.P. | 代理人 | Oblon, McClelland, Maier & Neustadt, L.L.P. |
| 主权项 | 1. A semiconductor memory device comprising: a memory cell array in which memory cells is provided in a matrix; word lines connected to the memory cells; bit lines connected to the memory cells; a control circuit configured to control potentials of the word lines and potentials of bit lines, a constant voltage generation circuit, wherein data in an n number of memory cells among the memory cells is simultaneously read from memory cell array; an h (2<h<n) number of memory cells among the n number of memory cells is used as flag cells, data of the flag cells is determined by a majority decision for the read data from the h number of memory cells, and in a read result of a k (k<n) number of memory cells among the read n number of memory cells, the read data from the k number of memory cells is converted based on data of the flag cells determined by a majority decision. | ||
| 地址 | Minato-ku JP | ||