发明名称 MULTIIFRAME SYNCHRONIZATION SYSTEM
摘要 PURPOSE:To use for a time-division switchboard, etc., a system of economical constitution which can shorten front and back protective times, by inserting a multi- frame-synchronous bit with a sequence relation with a sequence relation established into each frame. CONSTITUTION:In order to discriminate a frame number given to each frame within one multi-frame, a pattern (binary code) expressing the frame number using multi-frame synchronous bit 1 in each frame is inserted into each frame. When multi-frame synchronization can not be made, dissidence signal 17 is outputted from comparator circuit 9 to synchronization protective circuit 10, which generates its output 18 in case of a step out, so that selector 11 will be switched. At this time, since discrimination 9 whether a step out or not is done for each frame, front and back protective times are shortened remarkably and bit 1 expresses the frame number as it is, so that the hardware can be constituted economically.
申请公布号 JPS54102817(A) 申请公布日期 1979.08.13
申请号 JP19780009106 申请日期 1978.01.30
申请人 NIPPON TELEGRAPH & TELEPHONE 发明人 IMAGAWA HITOSHI;EGAWA TETSUAKI;KIKUCHI SHIROU
分类号 H04J3/06;H04Q11/04 主分类号 H04J3/06
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